[asahi kasei] [AK7730A] 2004/05 - 1 - 1. general description the AK7730A is a highly integrated audio processing ic, including a stereo 24-bit input a/d and on-chip dsp. high quality analog performance is provided by a ster eo a/d with 97db (48 khz) dynamic range. this a/d supports sampling frequencies from 8 khz to 96 khz. this device includes 72kbit sram for delayed audio data that is suitable for simulated surround like a hall simula tion. this programmable dsp part supports the sampling frequencies from 8 khz to 192 khz. the design allows up to 4608 execution lines per audio sample cycle at 8 khz, 768 at 48 khz, 192 lines at 192 khz with multiple functi ons per line. the AK7730A can be used to implement complete sound field control, such as echo, 3d, parametric equalization, etc. it is packaged in a 48-lead lqfp package. 2. features dsp: - word length: 24-bit (data ram) - instruction cycle time: 27ns (768fs, fs=48khz ) - multiplier: 24 x 16 40-bit - divider: 24 / 24 16-bit or 24-bit - alu: 34-bit arithmetic opera tion (overflow margin: 4bit) - 24-bit arithmetic and logic operation - shift+register: 1, 2, 3, 4, 6, 8 and 15 bits shifted left 1, 2, 3, 4, 8 and 15 bits shifted right - other numbers in parentheses are restricted. provided with indirect shift function - program ram: 768 x 32-bit - coefficient ram: 1024 x 16-bit - data ram: 256 x 24-bit - offset ram: 48 x 13-bit (6144 x 12-bit / 3072 x 24-bit / 4096 x 12-bit + 1024 x 24-bit ) - internal memory: 72kbit sram - sampling frequency: 8khz to 192khz - serial interface port for micro-controller - master clock: 768fs@48khz ( generated by pll from 256fs or 384fs ) - master/slave operation - serial signal input port ( up to 8 ch ): 16/20/24-bit : output port ( 8 ch ): 24-bit adc: 2 channels - 24-bit 64x over-sampling delta sigma - sampling frequency: 8khz to 96khz - dr: 97dba ( fs=48 khz full-differential input ) - s/n : 98dba ( fs=48 khz full-differential input ) - s/(n+d) : 92db ( fs= 48 khz full-differential input ) - digital hpf (fc = 1hz) - single-ended or full-differential input other - eeprom boot (optional selectable eeprom b oot between 2 different programs) - up to 3 external jump pins - crc error check function - lrclk and bitclk input a nd output for slave mode - power supply: +3.3v 0.3v - operating temperature range: -40 c~85 c - package: 48pin lqfp (0.5mm pitch) 24bit 2ch adc+ audio dsp ak7730 a
[asahi kasei] [AK7730A] 2004/05 - 2 - 3. block diagram 1) eesel=?l? * swia,swq4~swq1,swqa,swjx3~swjx1 * it is selected by control register. * position of switches are default setting. sdout4 sdout3 sdout2 sdout1 sdata vrefl vrefh ainr- ainr+ ainl- jx0 /sdin4a ainl+ vrefl vrefh ainr- ainr+ ainl- ainl+ adc sdin4 sdin1 sdin3 sdout4 sdout3 sdout2 sdout1 sdin2 sdin3/ jx1 sdin2 /jx2 sdin1 vcom vcom swq4 swqa swq3 swq2 swq1 swia dsp so rdy drdy so clko1 controller init_reset s_reset lrclk_o lrclk_i si sclk rq si sclk rq smode eesel *rdy *drdy eepif eest eesi eeck eeso eecs eead eesel smode *lrclk_i *lrclk_o s_reset init_reset note) c=?l?: a ? q c b q a *pin : in case of eesel=?l? common is selected this mode. pin1/ pin2 : bold style is default setting of common pin. *clko2 bitclk_o bitclk_i *bitclk_i *bitclk_o jx0 jx1 jx2 swjx0 swjx1 swjx2 *cs cs xti cks0 xto lflt cks1 lflt cks1 cks0 xti xto clko2 clko1 pll&driver this block diagram is a simplified illustration of the AK7730A; it is not a circuit diagram.
[asahi kasei] [AK7730A] 2004/05 - 3 - 2) eesel=?h? * swia,swq4~swq1,swqa,swjx3~swjx1 * it is selected by control register. * position of switches are default setting. sdout4 sdout3 sdout2 sdout1 sdata vrefl vrefh ainr- ainr+ ainl- jx0 /sdin4a ainl+ vrefl vrefh ainr- ainr+ ainl- ainl+ adc sdin4 sdin1 sdin3 sdout4 sdout3 sdout2 sdout1 sdin2 sdin3 /jx1 sdin2 /jx2 sdin1 vcom vcom swq4 swqa swq3 swq2 swq1 swia dsp pll & divider so rdy drdy so swee clko1 clko2/ eest controller eepi f eest init_reset s_reset bitclk lrclk si sclk rq si sclk rq smode eesel rdy/ eesi drdy/ eeck eesi eeck eeso eecs *eecs *eeso eeadr *eeadr eesel smode *lrclk *bitclk s_reset init_reset jx0 jx1 jx2 swjx0 swjx1 swjx2 xti cks0 xto lflt cks1 lflt cks1 cks0 xti xto clko2 clko1 note) c=?l?: a ? q c b q a *pin : in case of eesel=?l? common is selected this mode. pin1/ pin2 : bold style is default setting of common pin. this block diagram is a simplified illustration of the AK7730A; it is not a circuit diagram.
[asahi kasei] [AK7730A] 2004/05 - 4 - ? AK7730A dsp block diagram cp0,cp1 cram 1024 w x 16bit dp0,dp1 dram 256wx24bit mpx16 mpx24 ofram 48wx13bit x multipl 16bit x 24bit ? 40bit micon i/f control pram 768w x 32bit dec pc stack : 1level mul shift a alu 34bit overflow ma r g in: 4bit dr0~3 over flow data generato r division 24 24 ? 24or16 peak detecto r tmp 8 x 24bit serial i/f cbus(16bit) dbus(24bit) 40bit 24bit 34bit 34bit 24bit 2 x 24bit sdout4 dlram 6kwx12bit or 3kwx24bit ptmp ( lifo ) 6 x 24bit dlp0,dlp1 4kwx12bit & 1kwx24bit cmp(compress & expand) 2 x 24/20/16bit 2 x 24/20/16bit sdin3 2 x 24/20/16bit 2 x 24/20/16bit sdin1 sdin2 from adc or sdin4a 2 x 24bit sdout3 2 x 24bit sdout2 2 x 24bit sdout1 y dbus b
[asahi kasei] [AK7730A] 2004/05 - 5 - 4. description of input/output pins (1) pin layout rq vcom vrefl bitclk_o/bitclk avss ainr- smode (top view) 48pin lqfp lrclk_i/lrclk clko2/eest bitclk_i/eeadr drdy/eeck rdy/eesi dvss dvdd cks1 sdout1 sdout4 dvdd sdin2/jx2 jx0/sdin4a dvdd dvss clko1 eesel bvss ainl+ ainr+ ainl- avss avdd vrefh sclk lflt note) *** is internal pull-down pin. 13 24 15 14 17 16 19 18 21 20 22 23 2 1 7 6 5 4 3 11 10 9 8 12 33 32 31 30 29 27 28 35 34 25 26 36 44 42 43 40 41 38 39 47 37 45 46 48 sdin3/jx1 xti xto lrclk_o/ eecs si so dvss sdin1 avdd sdout3 cks0 sdout2 cs /eeso init_reset s_reset
[asahi kasei] [AK7730A] 2004/05 - 6 - (2) pin function pin no. pin name i/o f unction classification 1 eesel i control mode select pin ( internal pull-down ) eesel=?l? : normal mode eesel=?h? : in case of self-boot up mode using akm product eeprom ak6510c,ak6512c eesel must be fixed ?l? or ?h? control 2 jx0/sdin4a i external conditional jump pin / dsp serial data input pin ( internal pull-down) * normally use as jx0 pin. * it can change its function as sdin4 by control register setting (swa,swjx0 ) it can input as serial input port comp atible with msb jus tified 24 bits / lsb justified 24, 20 and 16 bits. (normally this port is connected to adc serial output.) digital section conditional input / serial input data 3 sdin3/jx1 i dsp serial data input pin / external condition jump pin (internal pull- down ) * compatible with msb justified 24 b its / lsb justified 24, 20 and 16 bits. * it can change its function as a conditional jump pin jx1 by control register setting (swjx1). 4 sdin2/jx2 i dsp serial data input pin / external condition jump pin (internal pull-down ) * compatible with msb justified 24 b its / lsb justified 24, 20 and 16 bits. * it can change its function as a conditional jump pin jx2 by control register setting (swjx2). digital section serial input data / conditional input 5 sdin1 i dsp serial data input pin ( internal pull-down ) compatible with msb justified 24 bits / lsb justified 24, 20 and 16 bits. digital section serial input data 6 cks1 i master clock (xti) select pin ( internal pull-down ) normally, connect to dvss or open. control 7 bvss - silicon substrate potential 0v connect to avss. analog power suppl y 8 dvss - ground pin for digital section 0.0v 9 dvdd - power supply pin for digital section 3.3v(typ) digital power suppl y 10 sdout4 o dsp serial data output pin * outputs msb justified 24-bit data. * allows the selectable output from adc or sdin4a by control register settin g (swqa,swq4) 11 sdout3 o dsp serial data output pin * outputs msb justified 24-bit data. * allows the selectable output from sdin 3 by control register setting (swq3). 12 sdout2 o dsp serial data output pin * outputs msb justified 24-bit data. * allows the selectable output from sdin 2 by control register setting (swq2). 13 sdout1 o dsp serial data output pin * outputs msb justified 24-bit data. * allows the selectable output from sdin 1 by control register setting (swq1). digital section serial output data
[asahi kasei] [AK7730A] 2004/05 - 7 - pin no . pin name i/o func tion classification bitclk_i (eesel=?l?) i serial bit clock input pin slave mode: input 64 fs or 48 fs clocks. when it uses only for master mode then connect to dvss. (smode=?h?) system clock 14 eeadr (eesel=?h?) i eeprom address pin. ak6510c: eeadr=?l?. ak6512c: eeadr=?l? start address is 0000h eeadr=?h? start address is 1000h. eep lrclk_i (eesel=?l?) i lr channel select clock input pin. slave mode (smode=?l?) : input the fs clock. master mode (smode=? h?): connect to dvss. system clock 15 lrclk (eesel=?h?) i/o lr channel select clock pin slave mode (smode=?l?) : input the fs clock. master mode (smode=?h?) : output the fs clock. system clock bitclk_o (eesel=?l?) o serial bit clock output pin master mode (smode=?h?) : outputs 64fs clock. slave mode (smode=?l? ) : outputs bitclk_i clock. system clock 16 bitclk (eesel=?h?) i/o serial bit clock pin slave mode (smode=?l?) : inputs 64fs or 48fs clock. master mode (smode=?h? ) : outputs 64fs clock. system clock lrclk_o (eesel=?l?) o lr channel select clock output pin master mode (smode=?h?) : outputs the fs clock. slave mode (smode=?l?) : outputs lrclk_i clock. system clock 17 eecs (eesel=?h?) o eeprom chip select pin connect with cs pin of ak6510c/12c. eep rdy (eesel=?l?) o data write ready output pin for microcomputer interface. cs =?h? : hi-z microcomputer interface 18 rdy/eesi (eesel=?h?) o data write ready output pin for microcomputer interface / eeprom serial data output pin. connect with si pin of ak6510c/12c. after finished data transfer from eeprom (eest changes from?l? to?h?), this pin automatically changes its function as rdy pin. eep/ microcomputer interface drdy (eesel=?l?) o output data ready pin for microcomputer interface. cs =?h? : hi-z microcomputer interface 19 drdy/eeck (eesel=?h?) o output data ready pin for microcomputer interface / eeprom serial data output clock pin. connect to sck pin of ak6510c/12c. wh en eeprom data transfer finishes (eest changes from?l? to?h?), this pi n automatically changes function as drdy pin. eep/ microcomputer interface
[asahi kasei] [AK7730A] 2004/05 - 8 - pin no . pin name i/o func tion classification cs (eesel=?l?) i chip select pin for microcomputer interface. ( internal pull-down ) cs =?h? : si can not input, so,rdy.drdy = hi-z when eesel=?h?, this function does not work. microcomputer interface 20 eeso (eesel=?h?) i eeprom serial data receive pin ( internal pull-down ) connect to so pin of ak6510c/12c. eep 21 dvdd - power supply pin for digital section 3.3v (typ) 22 dvss - ground pin for digital section 0v power supply 23 clko1 o clock output pin output frequency can selectable by control register. system clock clko2 (eesel=?l?) o clock output pin output frequency can selectable by control register. system clock 24 eest (eesel=?h?) o eeprom write status pin the level of this pin changes from ?l? to ?h? when data transfer finishes fro m eeprom. it indicates the interface for the microcomputer is available. eep 25 xto o crystal oscillator output pin when crystal oscillator is used, it s hould be connected between xti and xto when the external clock is used, keep this pin open. 26 xti i master clock input pin connect a crystal oscillator between this pin and the xto pin, or input the external cmos clock signal to xti pin. system clock 27 dvss - ground pin for digital section 0v 28 dvdd - power supply pin for digital section 3.3v (typ) digital power supply 29 smode i slave / master mode selector pin smode=?l?: slave mode. smode=?h?: master mode. control 30 so o serial data output pin for microcomputer interfaces. 31 si i microcomputer interface serial data i nput and serial data output control pin. when si does not use, leave si = ?l?. 32 sclk i microcomputer interface serial data clock pin. when sclk does not use, leave sclk=?h? 33 rq i microcomputer interface write request pin. rq =?l?: microcomputer interface enable. however, when run-time data update: rq =?h?. when microcomputer interface does not use, leave rq =?h?. microcomputer interface. 34 s_reset i system reset pin 35 init_reset i reset pin ( for initialization) use initialization of the AK7730A. wh en changing cks1 or cks0 and changing xti input frequency, th is pin setting is necessary. reset 36 cks0 i master clock (xti) select pin ( internal pull-down ) control
[asahi kasei] [AK7730A] 2004/05 - 9 - pin no . pin name i/o func tion classification 37 lflt - filter connection pin for pll when use the pll function connect with r (5.6k ? and c (6.8nf) in series an d down to the analog ground (avss). 38 avss - analog ground 0v 39 avdd - power supply pin for analog section 3.3v (typ) 40 avdd - power supply pin for analog section 3.3v (typ) 41 vrefh i analog reference voltage input pin . normally, connect to avdd, and connect 0.1 f and 10 f capacitors betwee n this pin and avss. 42 vcom o common voltage normally, connect to 0.1 f capacitor between this pin and avss. don?t connect outside circuits. 43 vrefl i analog reference voltage input pin for low-level. normally, connect to avss. 44 avss - analog ground 0v 45 ainr- i adc rch analog inverted input pin. 46 ainr+ i adc rch analog non-inverted input pin. 47 ainl- i adc lch analog inverted input pin. 48 ainl+ i adc lch analog non-inverted input pin. analog section note) do not leave open digital input pin except pu ll-down pins and bitclk_i, lrclk_i on master mode. (if you do not use pull-down pin, leave open or connects to dvss.) ex. cd / md (master equipment) dac (slave equipment) smode clko2 xti lrclk_o bitclk_o clk gen. lrclk_i bitclk_i a k7730a clko1 fig,1 connect with others
[asahi kasei] [AK7730A] 2004/05 - 10 - 5. absolute maximum rating (avss, bvss, dvss = 0 v: all voltages indicated are relative to the ground.) item symbol min max unit power supply voltage analog(avdd) digital(dvdd) |avss(bvss)-dvss| note 1) va vd ? gnd -0.3 -0.3 4.6 4.6 0.3 v v v input current (except for power supply pin ) iin - 10 ma analog input voltage ainl+,ainl-,ainr+,ainr-, vina -0.3 va+0.3 v digital input voltage vind -0.3 va+0.3 v operating ambient temperature ta -40 85 c storage temperature tstg -65 150 c note 1) avss(bvss) should be same level as dvss. warning: operation at or beyond these limits ma y result in permanent damage to the device. normal operations are not guaranteed under these critical conditions in principle. 6. recommended operating conditions (avss, bvss, dvss = 0 v: all voltages indicated are relative to the ground.) items symbol min typ max unit power supply voltage avdd dvdd va vd 3.0 3.0 3.3 3.3 3.6 va v v reference voltage (vref) vrefh note 1) vrefl note 2) vrh vrl va 0.0 v v note 1) vrefh normally connects with avdd. note 2) vrefl normally connects with avss note: the analog input voltage and output voltage are proportional to the vrefh-vrefl voltages.
[asahi kasei] [AK7730A] 2004/05 - 11 - 7. electric characteristics (1) analog characteristics (unless otherwise specified, ta = 25 c; avdd, dvdd = 3.3v; vrefh = avdd, vrefl = avss; bitclk = 64 fs; signal frequency 1 khz; measuring frequency = 20 hz to 20 kh z @48 khz, 20 hz~40 khz @96khz; adc with all differential input s, clko output = 18.432mhz; xt i = 18.432mhz, smode = ?h?) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) fs = 48khz (-1dbfs) (note1) fs = 96khz (-1dbfs) 82 92 88 db db dynamic range fs = 48khz (a filter) (note2) fs = 96khz 90 97 93 db db s/n fs = 48khz ( a filter ) fs = 98khz 90 98 93 db db inter-channel isolation (f=1khz) 90 105 db dc accuracy inter-channel gain mismatching 0.1 0.3 db gain drift 50 ppm/ c analog input input voltage (note3) 1.22 1.32 1.42 vp-p adc section input impedance (fs=48khz) (note 4) 95 k ? note 1) in case of using single-ende d input, this value is not guarantee. note 2) indicates s/(n+d) when -60 dbfs signal is applied. note 3) the full-scale ( ? ain = (ain+) - (ain-)) can be represen ted by (fs = (vrefh-vrefl) 0.4). (2) dc characteristics (vdd=avdd=dvdd=3.0~3.6v, ta=25 c) parameter symbol min typ max unit high level input voltage vih 80%vdd v low level input voltage vil 20%vdd v high level output voltage iout=-100 a low level output voltage iout=100 a voh vol vdd-0.5 0.5 v v input leak current note 1) input leak current (pull-down) note 2) input leak current (xti pin) iin iid iix 30 50 10 a a a note 1) the pull-down pins and xti pin are not included. note 2) the pull-down pins ar e 1, 2,3,4,5,6,20 and 36 pin. note: regarding the input/output levels in the text, the low level will be represented as "l" or 0, and the high level as "h" or 1. i n principle, "0" and "1" will be used to represen t the bus (serial/parallel) such as registers.
[asahi kasei] [AK7730A] 2004/05 - 12 - (3) current consumption (avdd=dvdd=3.0v~3.6v, ta=25 c; master clock (xti)= 18.432mhz=384fs[fs=48khz]; pll is in active mode. ) power supply parameter min typ max unit power supply current note 1) 1)normal speed a) avdd b) dvdd c) total(a+b) 15 50 65 ma ma ma 2)double speed a) avdd b) dvdd c) total(a+b) 16 55 71 ma ma ma 3)quadruple speed a) avdd b) dvdd c) total(a+b) 4 55 59 ma ma ma 4) 1)2)3) max note 2) a) avdd b) dvdd c) total(a+b) 23 77 100 ma ma ma 5) init_reset ="l" (reference) note 3) 4 ma power consumption 1)normal speed a) avdd b) dvdd c) total(a+b) 50 165 215 mw mw mw 2)double speed a) avdd b) dvdd c) total(a+b) 53 182 235 mw mw mw 3)quadruple speed a) avdd b) dvdd c) total(a+b) 13 182 195 mw mw mw 4) 1)2)3) max note 2) a) avdd b) dvdd c) total(a+b) 83 277 360 mw mw mw 5) init_reset ="l? ( reference) note 3) 13 mw note 1) varies slightly different according to th e system frequency and contents of the dsp program. note 2) max value is ?double speed? mode. note 3) this is a reference value in cas e of using the crystal oscillator. because most of the power current at the initial re set state is the oscillator section, the value may vary slightly according to the types of crystal oscillators and external ci rcuits. this is ?reference value? only.
[asahi kasei] [AK7730A] 2004/05 - 13 - (4) digital filter characteristics values described below are desi gn values cited as references. 1) adc section: (ta=25 c; avdd, dvdd =3.0v~3.6v; fs=48 khz; hpf=off note1)) parameter symbol min typ max unit pass band 0.005db note 2) (-0.02db) (-6.0db) pb 0 - - 21.768 24.00 21.5 - - khz khz khz stop band sb 26.5 khz pass band ripple note 2) pr 0.005 db stop band attenuation note3,4) sa 80 db group delay distortion ? gd 0 us group delay (ts=1/fs) gd 29.3 ts note 1) hpf response is not including. note 2) the pass band is from dc to 21.5 khz when fs = 48 khz. note 3) the stop band is from 26.5 khz to 3.0455mhz when fs = 48 khz. note 4) when fs = 48 khz, the analog modulator samples an alog input at 3.072mhz. the input signal is not attenuated by the digital filter in the multiple bands (n x 3.072mhz 21.99khz; n=0, 1, 2, 3...) of the sampling frequency.
[asahi kasei] [AK7730A] 2004/05 - 14 - (5) switching characteristics 5-1) system clock (avdd=dvdd=3.0v~3.6v,ta=-40~85 c,cl=20pf) parameter symbol min typ max unit master clock (xti) a) with a crystal oscillator: note.1) cks[1:0]=0h fmclk - 16.9344 18.432 - mhz cks[1:0]=1h fmclk - 11.2896 12.288 - mhz cks[1:0]=2h fmclk - 22.5792 24.576 - mhz b) with an external clock: note. 1) duty factor ( 18.5mhz) ( > 18.5mhz) 40 45 50 50 60 55 % % cks[1:0]=0h fmclk 16.0 18.6 mhz cks[1:0]=1h fmclk 11.0 12.4 mhz cks[1:0]=2h fmclk 22.0 24.8 cks[1:0]=3h fmclk 24.0 37.0 mhz clock rise time clock fall time tcr tcf 6 6 ns ns lrclk sampling frequency fs 8 48 192 khz slave mode :clock rise time slave mode :clock fall time tlr tlf 6 6 ns ns bitclk note 2) fbclk 48 64 fs slave mode: high level width slave mode: low level width tbclkh tbclkl 36 36 ns ns slave mode :clock rise time slave mode :clock fall time tbr tbf 6 6 ns ns note 1) only cks[1:0]=3h is not use pll. note 2) 48fs mode can be use only at slave mode. 5-2) reset (avdd=dvdd=3.0v~3.6v,ta=-40~85 c,cl=20pf) parameter symbol min typ max unit init_reset note 1) trst 400 ns s_reset trst 400 ns note 1) ?l? is acceptable when power is turned on, but ?h? needs stable master clock input.
[asahi kasei] [AK7730A] 2004/05 - 15 - 5-3) audio interface (avdd=dvdd=3.0~3.6v,ta=-40 c ~85 c,cl=20pf) parameter symbol min typ max unit slave mode bitclk frequency fbclk 48 64 fs bitclk low level width tbclkl 36 ns bitclk high level width tbclkh 36 ns delay time from bitclk" " to lrclk tblrd 20 ns delay time from lrclk to bitclk " " tlrbd 20 ns delay time from lrclk to serial data output tlrd 25 ns delay time from bitclk to serial data output tbsod 25 ns serial data input latch hold time tbsids 25 ns serial data input latch setup time tbsidh 25 ns master mode bitclk frequency fbclk 64 fs bitclk duty factor 50 % delay time from bitclk" " to lrclk note 1) tblrd 20 ns delay time from lrclk to bitclk" " note 1) tlrbd 20 ns delay time from lrclk to serial data output tlrd 25 ns delay time from bitclk to serial data output tbsod 25 ns serial data input latch hold time tbsids 25 ns serial data input latch setup time tbsidh 25 ns note 1) this feature is to avoid lrclk edge and bitclk " ?edge.
[asahi kasei] [AK7730A] 2004/05 - 16 - 5-4) microcomputer interface (avdd=dvdd=3.0v~3.6v, ta=-40~85 c, cl=20pf) parameter symbol min typ max unit microcomputer interface signal rq fall time twrf 8 ns rq rise time twrr 8 ns sclk fall time tsf 8 ns sclkrise time tsr 8 ns sclk low level width tsclkl 50 ns sclk high level width tsclkh 50 ns microcomputer to AK7730A time from reset " " to rq " " trew 200 ns time from rq " " to reset " " note 1) twre 200 ns rq high level width twrqh 200 ns time from rq " " to sclk" " twsc 200 ns time from sclk" " to rq " " tscw 6tmclk ns si latch setup time tsis 100 ns si latch hold time tsih 100 ns AK7730A to microcomputer time from sclk" " to drdy" " tsdr 3tmclk ns time from si" "to drdy" " tsidr 3tmclk ns si high level width tsih 3tmclk ns delay time from sclk" " to so output tsos 100 ns hold time from sclk" " to so output tsoh 150 ns AK7730A to microcomputer (ram data read-out) si latch setup time (si="h") trsish 30 ns si latch setup time (si="l") trsisl 30 ns si latch hold time trsih 30 ns time from sclk" " to so output tsod 100 ns AK7730A to microcomputer (crc result out) note 2) delay time from rq " " to so output trsoc 150 ns delay time from rq " " to so output note 3) tfsoc 50 ns cs (eesel=?l? or open) cs fall time tcsf 8 ns cs rise time tcsr 8 ns time from s_reset " " to cs " " twrcs 400 ns time from cs " " to s_reset " " twcsr 400 ns cs high level width twcsh 800 ns time from cs " " to rq " " twcsrq 400 ns time from rq " " to cs " " twrqcs 400 ns cs " " to so,rdy,drdy hi-z release (rl=10k ? ) tcshr 600 ns cs " " to so,rdy,drdy hi-z (rl=10k ? ) tcshs 600 ns eeprom to AK7730A(eesel=?h?) eeso latch setup time teesos 100 ns eeso latch hold time teesoh 100 ns note 1) except for external jump code set at reset state. note 2) in the case of the data of the surplus of serial data d(x) divided by g(x) is equal to r(x), then so = ?h?. note 3) this means th at it must read more than 50ns before rq falling .
[asahi kasei] [AK7730A] 2004/05 - 17 - (6) timing waveform 6-1) system clock 6-2) reset tcf tcr 1/fmclk 1/fmclk vih vil xti tlf tlr 1/fs 1/fs vih vil lrclk tbf tbr tbclkl tbclkh 1/fbclk 1/fbclk vih vil bitclk init_reset s_reset vil trst tbclk=1/fbclk tmclk=1/fmclk
[asahi kasei] [AK7730A] 2004/05 - 18 - 6-3) audio interface tbsidh tbsids tbsod tlrd tblrd tlrbd 50%dvdd 50%dvdd 50%dvdd 50%dvdd lrclk bitclk sdout sdout1,sdout2, sdout3,sdout4 sdin1,sdin2 sdin3,sdin4a
[asahi kasei] [AK7730A] 2004/05 - 19 - tsclkh tsclkl tsis tsih tscw twsc twrqh trew twre tscw 6-4) microcomputer interface ? microcomputer interface ? AK7730A ? microcomputer note: the timing of the run state is the same except s_reset is ?h?. sclk vih vil tsf tsr s_reset twsc rq sclk 50%dvdd 50%dvdd 50%dvdd 50%dvdd si rq vih vil twrf twrr
[asahi kasei] [AK7730A] 2004/05 - 20 - dvdd 50%dvdd dvss tsos dvdd 50%dvdd dvss 50%dvdd 50%dvdd tsih 50%dvdd dvdd 50%dvdd dvss tsos dvdd 50%dvdd dvss 50%dvdd 50%dvdd rq sclk si drdy 50%dvdd 50%dvdd dvss 50%dvdd s_reset rq sclk so si drdy s_reset so ? AK7730A ? microcomputer (dbus output) 1) dbus 24-bit output 2) dbus less than 24-bit ( in case of using si control ) tsdr tsidr
[asahi kasei] [AK7730A] 2004/05 - 21 - trsish trsih trsisl s_reset rq trsih trsisl ? AK7730A ? microcomputer (read out ram data) ? AK7730A ? microcomputer (crc check: {the surplus of d(x)/g(x)}=r(x) ) 50%dvdd dvss 50%dvdd dvss sclk si so 50%dvdd 50%dvdd 50%dvdd tsod rq trsoc so 50%dvdd 50%dvdd tfsoc
[asahi kasei] [AK7730A] 2004/05 - 22 - ? cs (eesel=?l? or open) ? eeprom ? AK7730A 50%dvdd 50%dvdd 50%dvdd s_reset twcsrq cs rq twrqcs twcsh twrcs twcsr tcsf tcsr tcshr tcshs vih 50%dvdd vil 90%dvdd 50%dvdd 10%dvdd cs so,rdy,drdy so,rdy,drdy cl rl rl measurement circuit dvdd eeck eeso 50%dvdd 50%dvdd teesos teesoh
[asahi kasei] [AK7730A] 2004/05 - 23 - 8. function description (1) various setting 1-1) smode: slave and master mode selector pin this pin setting decides lrclk and bi tclk to either inputs or outputs. a) slave mode: smode="l" lrclk (1fs) and bitclk (64fs or 48fs) become inputs. b) master mode: smode="h" lrclk (1fs ) and bitclk (64fs) become outputs. note) smode pin designed as fixed ?l? or ?h?. th erefore, after release th e initial reset( init_reset =?l? ?h?) this pin must change during the system reset state ( s_reset ="l") . especially , at the slave mode, it begins phase matching between internal and external clock by the release of sysytem reset (see (8.(4 )) resetting). do not change smode at runtime, it will cause an error. 1-2) cks1,cks0 : master clock (xti) select pin mode cks[1:0] clock series xti input frequency (mhz) xti available input frequency range (mhz) internal pll maximum number of dsp steps (fs=48khz) 0 0h 384fs series 18.432, 16.9344 16.0~18.6 use 768 1 1h 256fs series 12.288, 11.2896 11.0~12.4 use 768 2 2h 512fs series 24.576, 22.5792 22.0~24.8 use 768 3 3h 768fs series 36.864, 33.8688 24.0~37.0 not use 768 (xti=36.864mhz) note) cks1=cks[1],cks0=cks[0], mode 3 can not use crystal oscillator. mode 3 can not use the crystal oscillator. the maximum frequency of the mast er clock (mclk) is 36.864mhz. normally it will use mode 0 or 1.( when cks1 a nd cks0 leave open, it is selected mode 0. ) mode 2 is used when 512fs master clock must be supplie d. mode 3 is used when internal pll is not used. after power up, it should change the setting of cks1 and cks0 during the initial reset( init_reset =?l?, s_reset =?l?). because of cks1 and cks0 pins control internal pll circuit clock, the AK7730A may no operate correctly if these pins change i n runtime. xti frequency changes should al so be done during the initial reset. the sampling rate changing can be done by the control register setting. pll x2 mclk xti 18.432mhz / 16.9344mhz 36.864mhz / 33.8688mhz mode 0 pll x3 mclk xti 12.288mhz / 11.2896mhz 36.864mhz / 33.8688mhz mode 1 pll x3 mclk xti 24.576mhz / 22.5792mhz 36.864mhz / 33.8688mhz mode 2 mclk xti 36.864mhz / 33.8688mhz 36.864mhz / 33.8688mhz mode 3 1/2 fig. relationship of xti and mc lk (internal master clock)
[asahi kasei] [AK7730A] 2004/05 - 24 - (2) control registers the control registers can be set via the microcomputer interf ace in addition to the control pi ns. these 6 registers consist of 7-bit data however; sclk always needs 16bit clock (command code 8bit, data 8bit). each register is set after the last d0 data is written. for the value to be written in the control registers see the description of the inte rface with microcomputer. the fol lowing describes the control register map. these control registers are initialized by init_reset =?l?, but these are not initialized by s_reset ="l?. test: for test (input 0,x: it ignores input data, but should input 0). command code w r name d7 d6 d5 d4 d3 d2 d1 d0 60h 70h cont0 dfs2 dfs1 dfs0 difs dif1 dif0 setck x 00h 62h 72h cont1 dararam rm bank1 bank0 cmp_n ss1 ss0 x 00h 64h 74h cont2 psad swa swqa ssdin3 test test test x 00h 66h 76h cont3 swjx2 swjx1 swjx0 swq4 swq3 swq2 swq1 x 00h 68h 78h cont4 clk1e clk1s1 clk1s0 clk2e clk2s1 clk2s0 test x 00h 6ah 7ah cont5 swee setc1 setc2 test test test test x 00h 1. cont0 and cont5 can be set only at system reset ( s_reset ="l"). 2. cont1~4 should be set at system reset ( s_reset ="l?), otherwise an unwanted noise could be sent to the outputs. 3. test bit is used for test therefore set 0. 4. default setting is the same value that is initialized by initial reset ( init_reset =?l? ).
[asahi kasei] [AK7730A] 2004/05 - 25 - 2-1) cont0: sampling rate and initerface selection this register is enable only at system reset state ( s_reset =?l?). command code write read name d7 d6 d5 d4 d3 d2 d1 d0 default 60h 70h cont0 dfs2 dfs1 dfs0 difs dif1 dif0 setck x 00h c d7,d6,d5:dfs2,dfs1,dfs0 sampling rate setting. fs:sampling frequency cks[1:0] (input frequency of xti) mode dfs2 dfs1 dfs0 0h 1h 2h 3h fs(khz) dsp number of steps 0 0 0 0 384fs 256fs 512fs 768fs 48,44.1 768 1 0 0 1 192fs 128fs 256fs 384fs 96(,88.2) 384 2 0 1 0 96fs 64fs 128fs 192fs 192(,176.4) 192 3 0 1 1 576fs 384fs 768fs 1152fs 32(,29.4) 1152 4 1 0 0 1536fs 1024fs 2048fs 3072fs 12(,11.025) 3072 5 1 0 1 768fs 512fs 1024fs 1536fs 24(,22.05) 1536 6 1 1 0 1152fs 768fs 1536fs 2304fs 16(,14.7) 2304 7 1 1 1 2304fs 1536fs 3072fs 4608fs 8 4608 note 1) except mode 0~5 setting and sampling rate is prohibited. note 2) in case of select mode 2, it must set ?1? on cont2 psad(d7). d d4:difs audio interface selection 0: akm method 1: i 2 s compatible (in this case, all input / output pins are i 2 s compatible.) e d3,d2:dif1,dif0 sdin1,sdin2,sdin3,sdin4a input mode selector mode dif1 dif0 0 0 0 msb justified (24bit) 1 0 1 lsb justified (24bit) 2 1 0 lsb justified (20bit) 3 1 1 lsb justified (16bit) note) when d4= 1, the state is i 2 s compatible independently of mode setting, however set to mode 0. f d1: setck select output clock when the condition of cont5 setc1=1 or setc2=1 cont0 dfs2 dfs1 dfs0 dfs mode 0 1 2 3 4 5 6 7 setck=0 256fs n/a n/a 256fs 1024fs 1024fs 512fs 1024fs setck=1 64fs 64fs 64fs 64fs 256fs 256fs 128fs 256fs g d0: always 0 when inputs d0, cont0 setting is fixed. note) underline of the settings with ?_? mean default setting.
[asahi kasei] [AK7730A] 2004/05 - 26 - 2-2) cont1: ram control recommend this register changing at system reset state ( s_reset =?l?). command code write read name d7 d6 d5 d4 d3 d2 d1 d0 default 62h 72h cont1 dataram rm bank1 bank0 cmp_n ss1 ss0 x 00h note) in case of not using dlram, it should select mode 2 or 3 on d4,d5. c d7:dataram dataram add ressing mode selector 0: ring addressing mode 1: linear addressing mode dataram has 256-word x 24-bit and ha s 2 addressing pointer (dp0, dp1). the ring addressing mode: it?s starting addre ss increments by 1 every sample period. the linear addressing mode: its starting addr ess is always same, dp0 = 00h and dp1 = 80h. d d6:rm: decompress bit mode 0: sign bit 1: random data when it selects compress & decompress mode (d3:cm p_n = 0), this bit decides decompressed lsb bits. e d5,d4:bank[1:0] dlram setting mode bank1:d5 bank0:d4 memory 0 0 0 24bit 3kword(ram a) 1 0 1 12bit 6kword(ram a) 2 1 0 12bit 4kword(ram a),24bit 1kword(ram b) 3 1 1 24bit 1kword(ram a),12bit 4kword(ram b) note) when the mode 0 or 1 is selected, the pointer 0 and 1 are available for both ram area. when the mode 2 or 3 is selected, the pointer 0 is available for the ram a and the pointer is available for the ram b. in case of not using dlram, it should select mode 2 or 3. f d3:cmp_n 12bitdlram compress & decompress selector when mode 1,2 or 3 is selected, th is register can set up on or off of its compress/decompress function. 0: compress & decompress function on when it writes to dlram the dbus data is compressed to 12-b it and when it read from dlram, the data is depressed to 24-bit. 1: compress & decompress function off it always writes to dlram msb 12-bit of dbus data and it read from msb 12-bit of dlram and add to 000h for lsb bits. g d2,d1:ss[1:0] dlram setting of sampling timing (only for ram a) mode ss1:d2 ss0:d1 ram a mode selected by bank[1:0] 0 0 0 update every sampling time 1 0 1 update every 2 sampling time 2 1 0 update every 4 sampling time 3 1 1 update every 8 sampling time note) when the mode 1,2 or 3 is selected, it comes out aliasing. h d0: input always 0 when inputs d0, cont1 setting is fixed. note) underlines of the setting of ?_? mean default setting.
[asahi kasei] [AK7730A] 2004/05 - 27 - 2-3) cont2: adc control and others ( see 3.block diagram ) recommend this register changing at system reset state ( s_reset =?l?). command code write read name d7 d6 d5 d4 d3 d2 d1 d0 default 64h 74h cont2 psad swa swqa ssdin3 test test test x 00h c d7:psad 0:normal operation 1:adc power save in the case of not using adc, set this va lue to ?1? and adc will be in reset. this can be useful for saving power consumption. the digital output signals of adc will be 00000h. when changing to normal operation, set this value to ?0? at system reset. d d6:swa ( see 3. block diagram.) 0: normal operation (adc sdata connected to dsp sdin4 ) 1: jx0/sdin4a pin connected to dsp sdin4. e d5:swqa ( see 3. block diagram.) 0: in the case of swq4=1, jx0/ sdin4a pin connected to sdout4 1: in the case of swq4=1, adc sdata connected to sdout4. f d4: ssdin3 load source selector for dbus 0:dr2,dr3 through output 1:sdin3 digital input (lch,rch) g d3:test 0:normal operation 1:test mode (do not use this mode) h d2:test 0:normal operation 1:test mode (do not use this mode) i d1:test 0:normal operation 1:test mode (do not use this mode) j d0: always input 0 when inputs d0, cont2 setting is fixed. note): underlines of the setting of ?_? mean default setting.
[asahi kasei] [AK7730A] 2004/05 - 28 - 2-4) cont3 : internal path setting (see. 3.block diagram) recommend this register changing at system reset state ( s_reset =?l?). command code write read name d7 d6 d5 d4 d3 d2 d1 d0 default 66h 76h cont3 swjx2 swjx1 swjx0 swq4 swq3 swq2 swq1 x 00h c d7:swjx2 0:sdin2/jx2 pin uses as sdin2 pin (jx2=0) 1:sdin2/jx2 pin uses as jx2 pin. d d6:swjx1 0:sdin3/jx1 pin uses as sdin3 pin (jx1=0) 1:sdin3/jx1 pin uses as jx1 pin. e d5:swjx0 0:jx0/sdin4a pin uses as jx0 pin 1:jx0/sdin4a pin uses as sdin4a (jx0=0) f d4:swq4 0: output dsp sdout4 1:swqa=0; output jx0/sdin4a. swqa=1; output adc sdata. g d3:swq3 0:output dsp sdout3. 1:output sdin3/jx1. h d2:swq2 0:output dsp sdout2. 1:output sdin2/jx2 i d1:swq1 0:output dsp sdout1. 1:output sdin1 j d0: always input 0 when inputs d0, cont3 setting is fixed. note) underlines of the setting of ?_? mean default setting.
[asahi kasei] [AK7730A] 2004/05 - 29 - 2-5) cont4:clko1,clko2 setting 1 recommend this register changing at system reset state ( s_reset =?l?). command code write read name d7 d6 d5 d4 d3 d2 d1 d0 default 68h 78h cont4 clk1e clk1s1 clk1s0 clk2e clk2s1 clk2s0 test x 00h noise may comes out when it changes clko1 or clko2. once clko1 or clko2 outputs, it can not stop without clk1e =1, clk2e =1 setting or initial reset. c d7: clk1e clko1 output control 0: clko1 outputs clock select ed by clk1s1 and clk1s0 1: clko1 outputs ?l?. d d6,d5:clk1s1,clks0 clko1 output clock select. mode clk1s1 clk1s0 clko1 0 0 0 mclk/2 1 0 1 mclk/3 2 1 0 mclkx2/9 3 1 1 test note1) mclk is an internal clock. mclk is changed by the input frequency of the xti. normaly mclk=36.864mhz or 33.8688mhz. see (5) sy stem clock 1) master clock select table. note2) it is time from init_reset release to clock begins to output. cks[1:0]=0h(xti=18. 432mhz) : 15ms(max) cks[1:0]=1h(xti=12. 288mhz) : 22ms(max) cks[1:0]=2h(xti=24. 576mhz) : 22ms(max) e d4: clk2e clko2 output control 0: clko2 outputs clock select ected by clk2s1 and clk2s0. 1: clko2 outputs ?l?. f d3,d2:clk2s1,cl2s0 clko2 output clock select mode clk2s1 clk2s0 clko2 0 0 0 mclk/2 1 0 1 mclk/3 2 1 0 mclkx2/9 3 1 1 test note : same as note1) and note2) of d . g d1:test 0:normal operation 1:testmode (do not use this mode ) h d0: always input 0 when inputs d0, cont4 setting is fixed. note) underlines of the setting of ?_? mean default setting.
[asahi kasei] [AK7730A] 2004/05 - 30 - 2-6) cont5: clko1,clko2 setting 2 this register is enabled only at system reset state ( s_reset =?l?). command code write read name d7 d6 d5 d4 d3 d2 d1 d0 default 6ah 7ah cont5 swee setc1 setc2 test test test test x 00h note) set this register after setting cont0. c d7: swee select clko2 output 0: clko2(@eesel=?l?),eest(@eesel=?h?) 1: clko2(@eesel=?l? or ?h?) d d6: setc1 0: output clko1 clock that select ed by cont4 clk1s1 and clk1s0 1: output clko1 clock that selected by cont0 setck note) when setc1 selected ?1?, clko1 outputs clock that setck setting by the system reset release. when changing this register, it comes out click noise at clko1. when clko1 outputs, it can not stop until clk1e =1 or initial reset. ( clock is requied.) e d5: setc2 0: output clko2 clock that sel ected by cont4 clk2s1 and clk2s0 1: output clko2 clock that selected by cont0 setck note) when setc2 selected ?1?, clko2 outputs clock that setck setting by the system reset release. when changing this register, it comes out click noise at clko2. when clko2 outputs, it can not stop until clk2e =1 or initial reset. ( clock is requied.) even in eesel=?h? condition, if setc2=1 then setc2 setting is valid. f d4:test 0:normal operation 1:testmode (do not use this mode ) g d3:test 0:normal operation 1:testmode (do not use this mode ) h d2:test 0:normal operation 1:testmode (do not use this mode ) i d1:test 0:normal operation 1:testmode (do not use this mode ) j d0: always input 0 when inputs d0, cont5 setting is fixed. note) underlines of the setting of ?_? mean default setting.
[asahi kasei] [AK7730A] 2004/05 - 31 - (3) power supply startup sequence at the rising of avdd and dvdd, init_reset and s_reset should be set to ?l?. init_reset = ?l? makes all control registers initialize. note 1), note 2). then the vref (anal og reference level) of the AK7730A is set up and it begins to generate in ternal master clock by setting to init_reset = ?h?. the interface of the AK7730A cannot accept before pll locks. so, it mu st wait at least 22ms from init_reset = ?h?. note 3) normally, init_reset setting is only done at turn on power. note 1): to confirm initialization it requires power up and master clock (xti) supplied. note 2): set to init_reset = ?h? after setting the oscillation wh en a crystal oscillator is used. this setting time may differ depending on the crys tal oscillator and its external circuit. note 3): in case of cks[1:0] = 0h then waiting time is 15ms. cks[1:0] = 1h or 2h then waiting time is 22ms. note: do not stop the system clock (s lave mode: xti, lrclk, bitclk, master mode: xti) except when s_reset = "l". if these clock signals are not supplied, exce ss current will flow due to dynamic logic that is used internally, and an operatio n failure may result. don?t set s_reset ="h" during init_reset ="l", unless its crystal oscillato r will stop or be in unstable. avdd dvdd init_reset s_reset when a crystal oscillator is used, ensure stable oscillation in this period. fig. power supply startup sequence power off before pll stable inhibit to transfer data (22ms) enable to transfer command or dsp program code. (internal pllclk ) xti clko1,clko2 clko output start 22ms(max)* 22ms(max)* : cks[1:0] = 1h or 2h ( 15ms : cks[1:0] = 0h )
[asahi kasei] [AK7730A] 2004/05 - 32 - (4) resetting the AK7730A has two reset pins: init_reset and s_reset . the init_reset pin is used to set up vref and in itialize the AK7730A, as shown in "power supply startup sequence section (3)." the system is reset when s_reset =?l?. (description of "reset" is for "system reset".) during a system reset, a program write operation is norma lly performed (except for write operation during running). during the system reset phase, the adc sections are also re set. (the digital section of adc output is msb first 00000h). however, vref will be active; lrclk and bi tclk in the master mode will be inactive . the system reset is released by setting s_reset to "h", which activates the internal counter. this counter generates lrclk and bitclk in the master mode: however, a problem may o ccur when a clock signal is generated. when the system reset is released in slave mode, internal timing will be actuated in synchronization with rising edge " ? " of lrclk (when the standard input format is used ). timing between the external and internal clocks is adjusted at this time. the refore make sure to avoid phase difference between lrclk and internal timing. if the phase difference in lrclk and internal timing is within about -1/16 to 1/16 of the input sampling cycle (1/fs) during the operation, the operation is performed with internal ti ming remaining unchanged. if the phase difference exceeds the above range, the phase is adjusted by synchronizing the " ? " of lrclk (when the standard input format is us ed). this prevents synchronization fa ilure with the external circuit. the adc section can output 516-lrclk after its internal counter ha s started. (the internal counter starts at the first rising edge of lrclk in master mode. in slave mode, it starts 2 lrclks after the release of system reset. ) the AK7730A performs normal operation when s_reset is set to "h".
[asahi kasei] [AK7730A] 2004/05 - 33 - (5) system clock 1) master clock select table. (a) sampling frequency 48khz series ( norm al :48khz, double:96khz, quadruple:192khz) xti input pin cks1 input pin cks0 cont0 dfs2 cont0 dfs1 cont0 dfs0 fs [khz] dsp step mclk [mhz] pll active ad active x?tal active 18.432 0 0 0 0 0 48 768 36.864 { { { 0 0 1 96 384 { { { 0 1 0 192 192 { { 0 1 1 32 1152 { { { 1 0 0 12 3072 { { { 1 1 1 8 4608 { { { 12.288 0 1 0 0 0 48 768 36.864 { { { 0 0 1 96 384 { { { 0 1 0 192 192 { { 0 1 1 32 1152 { { { 1 0 0 12 3072 { { { 1 1 1 8 4608 { { { 24.576 1 0 0 0 0 48 768 36.864 { { { 0 0 1 96 384 { { { 0 1 0 192 192 { { 0 1 1 32 1152 { { { 1 0 0 12 3072 { { { 1 1 1 8 4608 { { { 36.864 1 1 0 0 0 48 768 36.864 { 0 0 1 96 384 { 0 1 0 192 192 0 1 1 32 1152 { 1 0 0 12 3072 { 1 1 1 8 4608 {
[asahi kasei] [AK7730A] 2004/05 - 34 - (b) sampling frequency 44.1khz series (normal: 44.1khz, double: 88.2khz, quadruple:176.4khz) xti input pin cks1 input pin cks0 cont0 dfs2 cont0 dfs1 cont0 dfs0 fs [khz] dsp step mclk [mhz] pll active ad active x?tal active 16.9344 0 0 0 0 0 44.1 768 33.8688 { { { 0 0 1 88.2 384 { { { 0 1 0 176.4 192 { { 0 1 1 29.4 1152 { { { 1 0 0 11.025 3072 { { { 1 1 1 7.35 4608 { { { 11.2896 0 1 0 0 0 44.1 768 33.8688 { { { 0 0 1 88.2 384 { { { 0 1 0 176.4 192 { { 0 1 1 29.4 1152 { { { 1 0 0 11.025 3072 { { { 1 1 1 7.35 4608 { { { 22.5792 1 0 0 0 0 44.1 768 33.8688 { { { 0 0 1 88.2 384 { { { 0 1 0 176.4 192 { { 0 1 1 29.4 1152 { { { 1 0 0 11.025 3072 { { { 1 1 1 7.35 4608 { { { 33.8688 1 1 0 0 0 44.1 768 33.8688 { 0 0 1 88.2 384 { 0 1 0 176.4 192 0 1 1 29.4 1152 { 1 0 0 11.025 3072 { 1 1 1 7.35 4608 { (c) clko1,2 output select information xti input pin cks1 input pin cks0 cont5 setc1/ setc2 cont4 clk1s1/ clk2s1 cont4 clk1s0/ clk2s0 output clko1 clko2[mhz] 18.432 0 0 0 0 0 18.432 0 0 1 12.288 0 1 0 8.192 1 x x (256fs) 12.288 0 1 0 0 0 18.432 0 0 1 12.288 0 1 0 8.192 1 x x (256fs) 24.576 1 0 0 0 0 18.432 0 0 1 12.288 0 1 0 8.192 1 x x (256fs) 36.864 1 1 0 0 0 18.432 0 0 1 12.288 0 1 0 8.192 1 x x (256fs)
[asahi kasei] [AK7730A] 2004/05 - 35 - (d) clko1,2 output information clko1/clko2 init_reset s_reset clk1e / clk2e = 0 clk1e / clk2e = 1 l l stop - h l active stop h h active stop (e) output timing image the following figure indicates the timing of changing of clko1 and clko2. ( the phase of the clock is not always same as following figure.) example. setting of cont4 from 00h(default) to other. k si 68h 00100100 68h 10010000 sclk s_reset clko1 384fs 256fs stop clko2 fs=48khz,44.1khz rq 2) master clock (xti pin) the master clock is obtained by connecting a crystal oscillator be tween the xti pin and xto pin or by inputting an external clo ck into the xti pin while the xto pin is left open. 3) slave mode the required system clock is xti, l rclk (1 fs) and bitclk (48/64 fs). the master clock (xti) and lrclk must be synchronized, but the phase is not critical. 4) master mode the required system clock is xti. when the master clock (xti) is input, lrclk (1 fs) and bitclk (64 fs) will be outputted from the internal counter synchronized with the xti. lrclk a nd bitclk will not be active during initial reset ( init_reset ="l") and system reset ( s_reset ="l").
[asahi kasei] [AK7730A] 2004/05 - 36 - (6) audio data interface (internal connection mode) the serial audio data pins sdin1,sdin 2,sdin3,sdin4a,sdout1,sdout2, sdout3 and sdout4 are interfaced with the external system, using lrclk and bitclk. the ports sdina1, sd ina2, sdouta1, sdouta2, sdout d1 and sdoutd2 are not normally used. these ports are controlled via registers. ( see th e block diagram on page.2 and th e control register setting sec tion at page 28.) the data format is msb-first 2's complement . normally, the input/output format, in add ition to the standard format used by akm, can be changed to i 2 s compatible mode by setting the control register ?cont0 dif (d5) to 1?. (in this case, all input/output audio data pin interface are in the i 2 s compatible mode.) the input sdin1, sdin2, sdin3 and sd in4a formats are msb justified 24-bit at initialization. setting the control registers cont0: dif1 (d3), dif0 (d2) will cause these ports to be compatib le with lsb justified 24-bit, 20-bit and 16-bit. however, individual setting of sd in1, sdin2, sdin3 and sdin4a is not allowed. the output sdout1, sdout2, sdout3 and sdout4 are fixed at 24-bit msb justified only. in slave mode bitclk corresponds to not only 64fs but also 48fs. 64fs is the recommended mode. following formats describe 64fs examples. 1) standard input format (dif = 0: default set value) a) mode 1 (dif1, dif0 = 0, 0: default set value) * when you want to input the msb-justified 20-bit da ta into sdin, sdina input four "0" following the lsb. b) mode 2, mode 3, mode 4 sdin1,sdin2,sdin3,sdin4a mode2 : (dif 1,dif0)=(0,1) lsb justified 24-bit sdin1,sdin2,sdin3,sdin4a mode3 : (dif 1,dif0)=(1,0) lsb justified 20-bit sdin1,sdin2,sdin3,sdin4a mode4 : (dif 1,dif0)=(1,1) lsb justified 16-bit right ch left ch lrclk bitclk sdin1,sdin2, sdin3,sdin4a m : msb, l : lsb 10 9 8 7 6 4 53 0 21 31 30 29 31 30 29 10 9 8 7 6 4 5 3 0 2 1 2 1 l 22 m 21 2 1 l 22 m 21 right ch left ch lrclk bitclk sdin1,sdin2, sdin3,sdin4a don't care m : msb, l : lsb sdin1,sdin2 sdin3,sdin4a sdin1,sdin2 sdin3,sdin4a 31 30 23 22 21 20 19 17 18 16 15 0 1 31 30 23 22 21 20 19 17 18 16 15 m 22 21 20 19 17 18 16 15 m 22 21 20 19 17 18 16 15 0 1 l 1 l 1 don't care don't care don't care don't care don't care l 1 l 1 l 1 l 1 m 17 18 16 15 m17 18 16 15 m m
[asahi kasei] [AK7730A] 2004/05 - 37 - 2) i 2 s compatible input format (dif=1) mode 1: (dif1(d4),dif0(d3))=(0,0) must be set. 3) standard output format (dif=0: default set value) 4) i 2 s compatible output format (dif=1) right ch left ch lrclk bitclk sdin1,sdin2 sdin3,sdin4a m : msb, l : lsb 31 30 29 28 m 21 22 9 8 7 6 5 3 4210 31 30 29 28 2 l 1 m21 22 2l 1 9 8 7 6 5 3 4 2 1 0 right ch left ch lrclk bitclk sdout1 sdout2 sdout3 sdout4 m : msb, l : lsb m21 22 2l 1 m 21 22 2 l 1 31 30 29 31 30 29 9 8 7 6 5 3 4210 10 9 8 7 6 5 3 4 2 1 0 10 m : msb, l : lsb right ch left ch lrclk bitclk 31 30 29 28 m 21 22 m21 22 31 30 29 28 2 l 1 2l 1 9 8 7 6 5 3 4210 9 8 7 6 5 3 4 2 1 0 sdout1 sdout2 sdout3 sdout4
[asahi kasei] [AK7730A] 2004/05 - 38 - (7) interface with microcomputer the microcomputer interface uses 6 control pins; rq (request bar), sclk (serial data input clock), si (serial data input), so (serial data output), rdy (ready) and drdy (data ready). in the AK7730A, two types of operations are provided; writing and r eading during the reset phase (namely, system reset) and r/w during the run phase. during the reset phase, writing of the control register, program ra m, coefficient ram, offset ram, external conditional jump code, and reading of the program ram, coe fficient ram and offset ram, are enabled. during the run phase, writing of coefficient ram, offset ram a nd external conditional jump code, and reading of data on the dbus (data bus) from the so, is enabled. its data is msb first serial i/o. when the AK7730A needs to transfer data to the microcomputer, it starts by rq going ?l? expects reading of data on the dbus. the AK7730A reads si data at the rising point of sc lk, and outputs to so at the falling point of sclk. the AK7730A accepts first data as command then address data or some kinds of data input / output starts. when rq changes to ?h?, one command has fini shed. new command requests must set rq to ?l? again. for dbus data reads, leave rq =?h?. (it does not need command code input.) when it needs to clear the output buffer (micr), the si pin uses for control. (in this case, it is necessary to protect against a noise as sclk.) command code table is as follow. command code list command code conditions for use code name write read remark: cont0 60h 70h cont1 62h 72h cont2 64h 74h cont3 66h 76h cont4 68h 78h for the function of each bit, see the description of control registers. cont5 6ah 7ah pram c0h c1h cram a0h a1h ofram 90h 91h external condition jump c4h - reset phase crc check (r(x)) b6h d6h cont0~cont5 x 70h read available, same as reset code. cram rewrite preparation a8h - it needs to do before cram rewrite cram rewrite a4h - ofram rewrite preparation 98h - it needs to do before ofram rewrite ofram rewrite 94h - external condition jump c4h - same code as reset run phase crc check (r(x)) b6h d6h same code as reset note: do not send other than the above command codes. otherwise an operation error may occur. if there is no communication with the microcomputer, set the sclk to "h? and the si to "l" for use.
[asahi kasei] [AK7730A] 2004/05 - 39 - 1) write during reset phase a) control register write (during reset phase) the data comprises a set of 2 bytes used to perform control regi ster write operations (during rese t phase). when all data has been entered, the new data is sent at the rising edge of the 16 th count of sclk. data transfer procedure c command code 60h,62h,64h,66h,68h,6ah d control data (d7 d6 d5 d4 d3 d2 d1 d0) for the function of each bit, see the description of control registers, (section 2). control registers write operation note) it must be set always 0 to d0. rq s_reset 64h sclk si so 60h d7 ***d1 d0 d7 ***d1 d0
[asahi kasei] [AK7730A] 2004/05 - 40 - b) program ram writes (during reset phase) program ram write operations are performed during the reset phase using 7-bytes of da ta. when all data have been transferred, the rdy terminal is set to "l". upon completion of writing into the pram, rdy returns ?h? to allow the next data bit input. when writing to sequential addresses, input the data without a command code or address. to write discontinuous data, shift the rq terminal from "h" to "l" again and then input the comma nd code, address and data in that order. data transfer procedure c command code c0h ( 1 1 0 0 0 0 0 0) d address upper ( 0 0 0 0 0 0 a9 a8) e address lower (a7 . . . . . . . a0) f data (d31 . . . . . . d24) g data (d23 . . . . . . d16) h data (d15 . . . . . . d8) i data (d7 . . . . . . d0) input of continuous address data into pram 11000000 sclk si rdy so rq s_reset 000000a9a8 a7 ****a1a0 d31***** d0 d31***** d0 input of discontinuous address data into pram d31***d0 sclk si rdy so rq s_reset a7**a1a0 000000a9a8 11000000 a7**a1a0 000000a9a8 11000000
[asahi kasei] [AK7730A] 2004/05 - 41 - c) coefficient ram writes (during reset phase) 5 bytes of data are used to perform coefficient ram write operati ons (during reset phase). when all data has been transferred, the rdy terminal goes to "h". upon completion of writing into the cram, it goes to "h" to allow the next data to be input. when w riting to sequential addresses, input the data as shown below. to write discontinuous data, transition the rq terminal from "h" to "l" and then input the command code, address and data. data transfer procedure c command code a0h ( 1 0 1 0 0 0 0 0 ) d address upper ( 0 0 0 0 0 0 a9 a8) e address lower (a7 . . . . . . . a0) f data (d15 . . . . . . d8) g data (d7 . . . . . . d0) input of discontinuous address data into cram input of continuous address data into cram 10100000 sclk si rdy so rq s_reset 000000a9a8 a 7****a1a0 d15****d0 d15 **** d0 sclk si rdy so rq s_reset 10100000 000000a9a8 a7***a1a0 d15** d15 **** d0 10100000 000000a9a8 a7***a1a0
[asahi kasei] [AK7730A] 2004/05 - 42 - d) offset ram writes (during reset phase) 5 bytes of data are used to perform offset ram write operations (during reset phase). when all data has been transferred, the rdy terminal goes to "h". upon completion of writing into the ofram, it goes to "h" to allow the next data to be input. when writ ing to sequential addresses, input the data without a command code or address. to write discontinuous data, shift the rq terminal from "h" to "l" and then input the command code , address and data in that order. data transfer procedure c command code 90h ( 1 0 0 1 0 0 0 0 ) d address ( 0 0 a5 a4 .. . . a0 ) e data (0 0 0 0 0 0 0 0 ) f data (0 0 0 d12 d11 * * . d8 ) g data (d7 . . . . . . d0 ) input of data into ofram 10010000 sclk si rdy so rq s_reset 00000000 00a5****a0 d7****d1d0 000d12**** d8
[asahi kasei] [AK7730A] 2004/05 - 43 - e) external conditional jump code writes (during reset phase) two bytes of data are used to perform external conditional ju mp operations. the data can be entered during both the reset and operation phases, and the input data are set to the specified register at the leading edge of the lrclk. when all data bits ha ve been transferred, the rdy terminal goes to "l". upon write completi on, it goes to "h". a jump command will be executed if there is any one agreement between "1" of each bit of external condition code 8 bits (soft set) plus 3 b its (hard set) at the external input ter minal jx0, jx1,jx2 and "1" of each bit of the ifcon field. the data during the reset phase can be written only before release of the reset, after all data has been transferred. rq transition from "l" to "h" in the write operati on during the reset phase must be executed after three lrclk in the slave mode or one lrclk in master mode, resp ectively, from the trailing edge of the lrclk after release of t he reset. then the rdy goes to "h" after capturing the rise of th e next lrclk. a write operation from the microcomputer is disab led until the rdy goes to "h". the ifcon field provides external c onditions written on the program. it resets to 00h by init_rese t =?l?, however, it remains previous condition even s_reset =?l?. note: it should be noted that the lrclk phase is inverted in the i 2 s-compatible state. 7 0 jx0 jx1 jx2 external condition code ? ? ? ? ? ? ? ? ? ? ? ? check if there is any one agreement between the bit specified in ifcon and "1" in the external condition code 16 9 8 7 6 ifcon field ? ? ? ? ? ? ? ? ? ? ? data transfer procedure c command code c4h ( 1 1 0 0 0 1 0 0) d code data (d7 . . . . . d0) timing for external conditional jump write operation (during reset phase) rdy 11000100 si so sclk 2lrclk(max) lrclk l ch r ch rq s_reset d7 **** d0
[asahi kasei] [AK7730A] 2004/05 - 44 - 2) read during reset phase a) control register data read (during reset phase) to read data written into the control registers, input the command code and 16 bits of sclk. after the input command code, the data of d7 to d1 outputs from so is synchronized with the fa lling edge of sclk. d0 is inva lid, so please ignore this bit. data transfer procedure c command code 70h,72h,74h,76h,78h,7ah 70h (example) sclk si so d7 **** d1 d7 **** d1 rq s_reset 74h (example) reading of control register data
[asahi kasei] [AK7730A] 2004/05 - 45 - b) program ram read (during reset phase) to read data written into pram, input the command code and the a ddress you want to read out. after that, set si to "h" and sclk to "l". the data is then clocked out from so in sync hronization with the falling edge of sclk. (ignore the rdy operation that will occur in this case.) if there are continuous addresses to be read, repeat the above procedure starting from the step where si is set to "h". data transfer procedure c command code input c1h ( 1 1 0 0 0 0 0 1 ) d read address input msb ( 0 0 0 0 0 0 a9 a8) e read address input lsb (a7 . . . . a0) reading of pram data rdy 11000001 sclk si so d31 **** d0 rq s_reset 000000a9a8 a7 **** a1 a0 d31 **** d0
[asahi kasei] [AK7730A] 2004/05 - 46 - c) cram data read (during reset phase) to read out the written coefficient data, input the command code a nd the address you want to read out. after that, set si to "h" and sclk to "l?. the data is clocked out from so in sync hronization with the falling edge of sclk. if there are continuous addresses to be read, repeat the above procedure starting from the step where si is set to "h". data transfer procedure c command code a1h ( 1 0 1 0 0 0 0 1 ) d address upper ( 0 0 0 0 0 0 a9 a8) e address lower (a7 . . . . . . a0) reading of cram data rdy a7 **** a1a0 sclk si so d15 **** d0 rq s_reset 000000a9a8 10100001 d15 **** d0
[asahi kasei] [AK7730A] 2004/05 - 47 - d) ofram data read (during reset phase) the written offset data can be read out during the reset phase. to read it, input the command code and the address you want to read. after that, set si to "h" and sclk to "l". this co mpletes preparation for outputting the data. then set si to "l", an d the data is clocked out in synchronization with the falling edge of sclk. if there are continuous addresses to be read, repeat the abov e procedure starting from the step where si is set to ?h?. data transfer procedure c command code 91h ( 1 0 0 1 0 0 0 1 ) d address ( 0 0 a5 . . . . a0) reading of ofram data rdy 10010001 sclk si so d12*** d1 d0 rq s_reset 00 a5 **** a0 d12 *** d1 d0 d12 *** d1 d0
[asahi kasei] [AK7730A] 2004/05 - 48 - 3) write during run phase a) cram rewrites preparation and writes (during run phase) this function is used to rewrite cra m (coefficient ram) during program execu tion. after inputting the command code, you can input a maximum of 16 data (2 bytes 1set) of a continuous address you want to rewrite, then input the write command cod e and rewrite the leading address. every time the ram address to be rewritten is specified, the conten ts of ram are rewritten. the following is an example to show how five data bytes from address "10" of the coefficient ram are rewritten: coefficient ram execution address 7 8 9 10 11 13 16 11 12 13 14 15 rewrite position } } ? } } } note that address "13" is not executed until address "12" is rewritten. data transfer procedure * preparation for rewrite c command code a8h ( 1 0 1 0 1 0 0 0 ) d data ( d15 . . . . d8 ) e data ( d7 . . . . . d0 ) * rewrite c command code a4h ( 1 0 1 0 0 1 0 0 ) d address upper ( 0 0 0 0 0 0 a9 a8 ) e address lower (a7 . . . . a0 ) cram rewriting preparation and writing note: the rdy signal will go to high within the maximum of two lrclks if the rdylg width is programmed to ensure a new address to be rewritten within one sampling cycle. rdy 10101000 si so sclk max 200ns rdylg rq s_reset d15 **** d0 000000a9*a0 10100100
[asahi kasei] [AK7730A] 2004/05 - 49 - b) ofram rewrites preparation and writes (during run phase) this function is used to rewrite ofra m (offset ram) during program execution. after inputting the command code, you can input a maximum of 16 data (3 bytes 1 set) of a continuous address you want to rewrite. then input the write command code and rewrite the leading addre ss. every time the ram address to be rewritten is specified, th e contents of ram are rewritten. the following is an example to show how five data byte s from address "10" of the offset ram are rewritten: offset ram execution address 7 8 9 10 11 13 16 11 12 13 14 15 rewrite position } } ? } } } note that address "13" is not executed until address "12" is rewritten. data transfer procedure * preparation for rewrite c command code 98h ( 1 0 0 1 1 0 0 0 ) d data ( 0 0 0 0 0 0 0 0 ) e data ( 0 0 0 d12 . . . d8 ) f data ( d7 . . . . . . d0 ) * rewrite c command code 94h ( 1 0 0 1 0 1 0 0 ) d address ( 0 0 a5a4 . . . a0) rdy 10011000 si so sclk max 200ns rdylg rq s_reset 00 a5***a0 10010100 0**0d12 ** d0 note: the rdy signal will go to high within the ma ximum of two lrclks if the rdylg width is programmed to ensure a new address to be rewritten within one sampling cycle. ofram rewriting preparation and writing
[asahi kasei] [AK7730A] 2004/05 - 50 - c) external conditional jump code rewrite (during run phase) two data bytes are used to write an external conditional ju mp code. data can be input dur ing both the reset and operation phases, and input data is set to the specified register at the ri sing edge of lrclk. when all data has been transferred, the r dy terminal goes to "l". upon completion of writing, it goes to "h ". a jump command will be execute d if there is any one agreemen t between each bit of the 8-bit external condition code and "1"of each bit of the ifcon field. a write operation from the microc omputer is disabled until rdy goes to "h". note: the lrclk phase is inverted in the i 2 s-compatible state. data transfer procedure c command code c4h ( 1 1 0 0 0 1 0 0 ) d code data (d7 . . . . . d0) external condition jump write timing (during run phase) 11000100 si so sclk lrclk rdy l ch r ch max 2lrclk max0.25lrclk rq s_reset d7 *** d0
[asahi kasei] [AK7730A] 2004/05 - 51 - 4) read-out during run phase (so output ) a) control register data read (during run phase) the control register can read during run time. to read data written into the control registers, input the command code and 16 bits of sclk. after the input command code, the data of d7 to d1 outputs from so is synchronized with the falling edge of sclk. d0 is invalid, so please ignore this bit. data transfer procedure c command code 70h,72h,74h,76h,78h,7ah in order to know the each bit function, see 8. function description (2) control registers. 70h (example) sclk si so d7 **** d1 d7 **** d1 rq s_reset =?h? 74h (example)
[asahi kasei] [AK7730A] 2004/05 - 52 - b) so data read (during run phase) so outputs data on dbus (data bus) of the dsp section. data is set when @micr the dst field specifies. setting of data allows drdy to go to "h", and data is output synchronized with the falling edge of sclk . when si goes to "h", drdy goes to "l" to wait for the next command. once drdy goes to "h", the data of the last @micr command imme diately before drdy goes to "h" will be held until si goes to "h" or read out 24-bit data with sclk, and subsequent commands will be rejected. a maximum of 24 bits are output from so. note) in the case of read out 24-bit data, drdy falls down when 24 th sclk rising edge and so output bit is not stable. so, if the microcontroller cannot read out at sclk risi ng edge, it should ignore the last 1bit (d0). so read (during run phase) drdy sclk si so data1 @micr data2 d23 d22 d21* * * * * d3 d2 d1 d0 d23 d22 * * * * d16 d15 d14 rq s_reset 24 sclk clock less than 24 sclk
[asahi kasei] [AK7730A] 2004/05 - 53 - 5) simple error check for communication the AK7730A has a simple crc error check function. (note: its main purpose is checking against the noise effects during writes from microprocessor to the AK7730A. this check cannot guarantee 100% error detection on the AK7730A, because this crc (cyclic re dundancy check) is before writing internal AK7730A?s ram or its register. explanation: * serial data(x): input si data from rq fall to rise up. * generator polynomial g(x) =x 16 +x 12 +x 5 +1 (x.25 of ccitt standard order of hexadecimal is 11021h). * the rest of d(x) divides by g(x) is r(x). this division is using exclusive-or instead of subtraction during this calculation. it makes good 16-bit zero data after translated serial data d(x) and the rest r(x) of this division comes out 16bit data. in order to do simple error check is as following: 1) use the command code b6h and write the r(x) (the rest result of serial data d(x) divided by g(x)). 2) then use the command code d6h and read out r(x) to check wh ether the r(x) is correct or not. (unless this read out, crc check itself works.) 3) if the result of d(x) divided by g(x) is equal to r(x), so outputs ?h? from the next rising edge of rq to falling edge of rq . (however, so read out from micro-controller is prior to this signal. refrain from a runtime read out while doing crc check.) if r(x) is not equal to the result, it outputs ?l?. 4) if you want to check other serial data, then repeat action form 1) to 3). note) in the case of detecting crc error in runtime ?cram re write? (a4h) or ?ofram rewrite?(94h), the possibility of writing data to the wrong address exists. * specific order of data translates. 1) write the register the rest r(x) data writing is using 3-byte/unit (24bit) data translate order. c command code b6h d upper 8bit of r(x) (d15 * * * * * * d8) e lower 8bit of r(x) ( d7 * * * * * * d0) 2) read out the register the rest r(x) data reading out is 3-byte/unit (24bit) data translate order c command code d6h d upper 8bit of r(x) (d15 * * * * * * d8) e lower 8bit of r(x) ( d7 * * * * * * d0) rq sclk example: control register writing, reading si so d15 *** d0 r(x) d15 *** d0 d6h b6h
[asahi kasei] [AK7730A] 2004/05 - 54 - 3) crc check 4) example of the r(x) made from d(x). examples d(x) r(x) 1 d6abcdh 1e51h 2 d2a5a5h 0c30h 3 a855557777aaaa0000ffffh 2297h (8) adc high-pass filter the AK7730A incorporates a digital high-pass filter (hpf) for canceling dc offset in the adc. the hpf cut-off frequency is about 1 hz (fs = 48 khz). this cut-off freque ncy is proportional to the sampling frequency (fs). 96khz 48khz 44.1khz 32khz 8khz cut-off frequency 1.86hz 0.93hz 0.86hz 0.62hz 0.16hz d15*** d0 d(x) the rest (d(x)/g(x))=r(x) the rest of d(x)/g(x)=r(x) crc check example. rq sclk si so 10100000 a7***a1 a0 000000a9a8 b6h r(x) rest of d(x)/g(x)
[asahi kasei] [AK7730A] 2004/05 - 55 - (9) interface for the eeprom 1) how to use AK7730A has an interface for the eeprom. after release of initial reset, it can load the data of pram, cram, ofram and its control register setting value automatically. th is function can save the memory area of microcomputer. the proper eeprom is the akm ak6510c or ak6512c. in case of using this function, it should wr ite a data as 2) program map of eeprom. how to use this function is as following ; at first set the eesel to ?h?, ( after crystal oscillator start, in case of using cr ystal ), then init_reset pin sets to ?h?. by this action, the internal counter starts to work and the AK7730A generate the control signal eecs , eesk and eesi for eeprom. then the AK7730A is load ed the data from eeso pin of the eeprom. when it finishes all data reading, then eesk and eesi change to ?l? and eecs changes to ?h?. eest pin changes from ?l? to ?h? to signify the finish of loading. after eest changes from ?l? to ?h?, the microcomputer interface pi ns are able to use even if eesel pin leaving ?h?. in case of reload again, leave eest ?h? and cont rol the initial reset pin, ( after sets init_reset =?l? then sets init_reset =?h? again.) in case of using the ak6512c, it can set another program fo r writing in 1000h of eeprom address. the eeadr pin can use for this selection. for error check, it can write r(x) (16bit) on crcdata of the program map address 0000h to 0ffbh. by writing this data it can check the error of data transfer from eeprom to AK7730A. afte r loading (eest = ?h?), so pin output ?h? if crc data is corre ct otherwise so outputs ?l?. so, so output ?l ? means data loading is not correct. ( generator polynomial g(x) =x 16 +x 12 +x 5 +1 (x.25 of ccitt standard order of hexadeci mal is 11021h).the rest of d(x) divides by g(x) is r(x). see page 52) when the AK7730A power up and initial rese t is released in eesel=?h? and s_reset =?h? condition, during eeprom download, internal system reset is active and after loading all data, then system reset releases automatically. this function m akes it possible to self boot up without microcomputer.
[asahi kasei] [AK7730A] 2004/05 - 56 - 2) program map for eeprom eepromaddress data note 0000h c0h pram write command code 0001h 00h pram address msb side 0002h 00h pram address lsb side 0003h pram0 data31-24 pram address 0 msb 8bit data 0004h pram0 data23-16 pram address 0 msb-1 8bit data 0005h pram0 data15-8 pram address 0 msb-2 8bit data 0006h pram0 data7-0 pram address 0 lsb 8bit data 0007h pram1 data31-24 pram address 1 msb 8bit data ???. ????.. ?????? 0bfeh pram766 data7-0 pram address 766 lsb 8bit data 0bffh pram767 data31-24 pram address 767 msb 8bit data 0c00h pram767 data23-16 pram address 767 msb-1 8bit data 0c01h pram767 data15-8 pram address 767 msb-2 8bit data 0c02h pram767 data7-0 pram address 767 lsb 8bit data 0c03h a0h cram write command code 0c04h 00h cram address msb side 0c05h 00h cram address lsb side 0c06h cram0 data15-8 cram address 0 msb 8bit data 0c07h cram0 data7-0 cram address 0 lsb 8bit data 0c08h cram1 data15-8 cram address 1 msb 8bit data ????.. ????. ?????. 0f59h cram425 data7-0 cram address 425 lsb 8bit data 0f5ah cram426 data15-8 cram a ddress 426 msb 8bit data 0f5bh cram426 data7-0 cram address 426 lsb 8bit data 0f5ch 90h ofram write command code 0f5dh 00h ofram address 0f5eh ofram0 data23-16 ofra m address 0 msb 8bit data 0f5fh ofram0 data15-8 ofram address 0 msb-1 8bit data 0f60h ofram0 data7-0 ofram address 0 lsb 8bit data 0f61h ofram1 data23-16 ofram a ddress 1 msb 8bit data ???? ?????.. 0feah ofram46 data7-0 ofram address 46 lsb 8bit data 0febh ofram47 data23-16 ofram address 47 msb 8bit data 0fech ofram47 data15-8 ofram address 47 msb-1 8bit data 0fedh ofram47 data7-0 ofram address 47 lsb 8bit data 0feeh 60h cont0 write command code 0fefh data cont0 data 0ff0h 62h cont1 write command code 0ff1h data cont1 data 0ff2h 64h cont2 write command code 0ff3h data cont2 data 0ff4h 66h cont3 write command code 0ff5h data cont3 data 0ff6h 68h cont4 write command code 0ff7h data cont4 data 0ff8h 6ah cont5 write command code 0ff9h data cont5 data 0ffah 00h reserve 0ffbh 00h reserve 0ffch b6h crc write command code 0ffdh crc data15-8 crc msb 8bit data 0ffeh crc data7-0 crc lsb 8bit data 0fffh 00h reserve
[asahi kasei] [AK7730A] 2004/05 - 57 - 9. system design (1) connection example rq dvdd 0.1 digital +3.3v 9 10 sdin1 lrclk_i bitclk_i xto xti rd cd cd 5 15 14 25 26 clko1 23 sdout1 35 drdy rdy si sclk so 19 30 18 33 31 32 micom i/f avss 38,44 avss ainr+ 46 ainl+ 48 ainl- 47 ainr- 45 38 39,40 analog +3.3v init_reset 34 s_reset 13 avdd dvss reset control 8,22,27 AK7730A vrefl 43 0.1 10 analog lch+ analog lch- analog rch+ analog rch- 7 bvss vrefh 41 vcom 42 0.1 0.1 0.1 jx0 2 smode 29 0.1 10 sdout2 12 sdout3 11 sdout4 10 sdin2 4 sdin3 3 clko2 24 bitclk_o 16 lrclk_o 17 lflt 37 6.8n 5.6k 21 28 dvdd dvdd cs 20
[asahi kasei] [AK7730A] 2004/05 - 58 - (2) peripheral circuit 1) connect with eeprom micro cmp si lrclk_o/ eecs rdy/eesi drdy/eeck AK7730A sclk so init_reset s_reset si sclk so rdy drdy clko2/eest micro cmp eeprom si eest rdy/eesi drdy/eeck AK7730A sclk so si ck so si sclk so rdy drdy clko2/eest eeprom si rdy/eesi drdy/eeck AK7730A sclk so si ck so clko2/eest cs h h h l 4line control 4line control + eeprom eeprom only eesel h eesel h eesel rq cs /eeso init_reset s_reset rq init_reset s_reset rq rq s_rst rq s_rst cs cs cs /eeso cs /eeso lrclk_o/ eecs lrclk_o/ eecs l reset control reset control reset control
[asahi kasei] [AK7730A] 2004/05 - 59 - 2) ground and power supply to minimize digital noise coupling, avdd and dvdd should be individually de-c oupled at the AK7730A. system analog power is supplied to avdd. generally, power supply and ground wires must be connected separately according to the analog and digital systems. connect them at a position close to the power source on the pcb board. decoupling capacitors and ceramic capacitors of small capacity in particular, should be connected at positions as close as possible to the AK7730A. 3) reference voltage the input voltage difference between the vrefh pin and the av ss pin determines the full scal e of analog input. normally, connect avdd to vrefh, and connect 0.1 f ceramic capacitors from them to avss. to shut out high frequency noise, connect a 0.1 f ceramic capacitor in parallel with an appropriate 10 f electrolytic capacitor between this pin and avss. the ceramic capacitor in particular should be connected as clos e as possible to the pin. to avoid coupli ng to the AK7730A, digital signals and clock signals should be kept away as far as possible from the vrefh pin. vcom is used as the common voltage of the analog signal.to shut out high fre quency noise, connect a 0.1 f ceramic capacitor in parallel with an appropriate 10 f electrolytic capacitor between this pin and avss. the ceramic capacitor should be connected as close as possible to the pin. do not draw current from the vcom pin. 4) analog input analog input signals are applied to the modulator through the di fferential input pins of each channel. the input voltage is equal to the differential voltage between ain+ and ain- ( ? vain = (ain+) - (ain-)), and the input range is fs = (vradh - vradl) 0.4. when vradh = 3.3v and vradl = 0v, the input range is within 1.32v. th e output code format is given in terms of 2's complements. when fs = 48 khz, the AK7730A samples the analog input at 3. 072 mhz. the digital filter eliminates noise from 30 khz to 3.042 mhz. however, noise is not rejected in the bandwidth close to 3.072 mhz. most audio signals do not have large noise in t he vicinity of 3.072 mhz, so a simple rc filter is sufficient. the analog source voltage to the AK7730A is +3.3v(typ.). voltage of avdd + 0.3 v or more, voltage of avss - 0.3 v or less, and current of 10 ma or more must not be applied to anal og input pins (ainl and ainr). excessive current will damage the internal protection circuit and will cause latch-up, thereby da maging the ic. accordingly, if the surrounding analog circuit v oltage is 15 v, the analog input pins must be protected from signals with the absolute maximum rating or more.
[asahi kasei] [AK7730A] 2004/05 - 60 - fig. 1 example of input buffer circuit (differential input) fig. 2 example of input buffer circuit (single ended input) an analog signal can be applied to the AK7730A is single ended mode. in this case, apply th e analog signal (the full scale is 2.64vpp when the internal reference voltage is used) to the ain-input, and bias to th e ain+input. however, use of a low satura ted operational amplifier is recommended if the operational amplifier is driven by the 3. 3-volt power supply. the electrolytic cap acitor connected to ain+ is effective for reducing the second harmonics. (see fig. 2.) 5) connection to digital circuit to minimize the noise resulting from the digital circuit, connect low voltage logic to the digital output. the applicable logi c family includes the 74lv, 74lv- a, 74alvc and 74avc series. vop = va+ = 3.3v njm2100 ain+ 3.3nf 330 330 10k 10k 4.7k 4.7k 0.1 ain- s ignal bias + - + 10 2.64vpp vop vop 10 + avss bias avss bias avss vop = va+ = 3.3v njm2100 ain+ 1.5nf 330 330 10k 10k 10k 10k 4.7k 4.7k 0.1 ain- signal bias + - - + + 10 1.32vpp 1.32vpp vop vop avss avss bias avss bias
[asahi kasei] [AK7730A] 2004/05 - 61 - 10. package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit:mm) 0.10 37 24 25 36 0.16 0.07 1.4typ 0.13 0.13 1.7max 0 10 0.10 m 0.5 0.2 0.5 z material & lead finish package: epoxy lead-frame: copper lead-finish: soldering plate
[asahi kasei] [AK7730A] 2004/05 - 62 - 11. marking a km a k7730avt xxxxxxx 1 1) pin #1 indication 2) date code: xxxxxxx (7 digits) 3) marking code: AK7730Avt 4) asahi kasei logo important notice z these products and their specifications are s ubject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd.(akm) sales office or authorized distributor concerning their current status. z akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, cu rrency exchange, or strategic materials. z akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, excep t with the express written consent of the representative director of akm. as used here: (a): a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to functi on or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b): a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indir ectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. z it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions , and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said pr oduct in the absence of such notification.
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